4DSP Products Technical support

Hello,


I have changed my fmc150 stellar ip star removing the waveform memory from DAC. Now i want to conect the ouput from ADC to DAC, which is easy to do in Stellar Ip.
Now i'm having a problem because i want to send a "copy" from the data that is passing from ADC to DAC, to zedbhost_if. I want to use the existing router, so can i just connect the output from ADC to both DAC input and router input?

I have another problem with the FMC15xAPP that i have modified. I programmed the board with the go *.bit file and everything went okay, the autonegotiation was okay too, but when i run the APP it always say "Could not open device 1000"


I already tried your APP and your bit file and it shows the samething. What is causing this issue?

Thanks

Ise simulation?


But i changed the frequency, changing the Fmc15xApp code.

The ADC errors might be because the IODELAY need to change when the frequency changes.


I suggest you run the simulation with your changes and see if that is working.

I used your ref design as you gave, the only thing that i have changed was the adc frequency to be equal to the DAC. So i made the DAC phy freq and ADC phy freq the same.


The files and the frequencies are attached. It give some pattern erros and i don't know why.

Dear Joao,


Can you post your txt file when you change the DAC clock? I am not sure I can do much but at least point out obvious things. Can you also in the same time tell me what are you output frequencies from the clock tree reported by the application, for DAC PHY and DAC REF. Can you also let me know if you have changed anything around the interpolation settings in the DAC?


Thanks,
Arnaud

Hello


I finally got the cables to make some experiments.


And with your current design i could see in the txt files the samples inputed in the DAC and the samples outputed from ADC. I compared the samples from both files and i saw that the frequency from the output digital sinewave of ADC was half of the input digital sinewave in DAC.


But that makes sense because the ADC is working two times faster then DAC.


So i already have been looking the clocktree and i was able to reduce the ADC sample frequency to make it equal to the DAC sample frequency. After that i run the APP with that differences and what i get in the adc txt files is completely different from what is supposed.


I don't know why when ADC and DAC are playing with the same sample frequency the results are wrong...

Dear Sir,


Let me try to formulate a few pointers for you. Both DAC and ADC clocks are coming from the clock tree device. I might be wrong, I haven't looked much around the design aspects but I believe the interpolation in the DAC is set to 4x because the ADC is running twice as fast and there is a dual data rate bus in the line.


I am not sure what is the maximum DAC speed on the FMC150 maybe you cannot double it up. Then you would want to get the ADC clock half down.




I hope that helps!


Best Regards,
Arnaud

Well, i was studying my problem and i concluded that the ADC is working at 250 MHZ and the DAC is working at 125 MHZ.


Now, i'm trying to understand how i should proceed to make the sample frequency equal.

Dear Sir,


I appreciate the fact I could not do more as per our policy and regulation but I want to followup with you. Are you able to move forward?


Best Regards,
Arnaud

Dear Sir,


Are you able to move forward? Is there anything I can do in more?


Best Regards,
Arnaud

I'll try to figure out on my own

Dear Sir,


As explained already, modifications done of the free of charge reference design are not supported by standard technical support. You will need to purchase an engineering support contract to get detailed help as per your expectations.


At this stage I think you should try and experiment because this is part of engineering. Maybe it sounds a bit short but we have sold more than 7000 FMC150s over the last 4 years and other customers where able to integrate this hardware solely referring to the FMC150 User Manual.


If you want everything done easy and step by step guidance on how to modify the reference design, an engineering support contract is required. Are you interested by this path?


Best Regards,
Arnaud

Hum ok but the FMC150 user manual doesn't describe clearly that work.
I read that we can give an external clock, we can use it as sampling clock for both ADC and DAC?


[list]
[li][font=verdana][size=78%]And is it possible to have some kind of document where you do a loopback between ADC and DAC to understand that better?[/size][/font][/li]
[li][font=verdana][size=78%]I attached a photo of the frequencies given in FMC15xAPP that frequencies shows that ADC and DAC are the same?[/size][/font][/li]
[/list][font=verdana][size=0.7em]Probably these questions are pretty obvious for you, but for the people trying to learn about your firmware these questions are not clear.[/size][/font]

Dear Sir,


It will be extremely difficult to modify the design if you don't understand the hardware architecture first. You need to first look at the DAC (DAC3283) and ADC (ADS62P49) integrated circuits in order to check its operation modes. The DAC has interpolation modes so you can have the DAC running twice as fast as the ADC clock. The the clock tree device, the CDCE72010 is in charge of dividing the VCO loop's output frequency by n. Figure 5 in the FMC150 user manual provides a diagram of the clock tree.


Chapter 5 of the user manual describes how to control the FMC150.


If you are interested, 4DSP can develop such a firmware, the ADC go to the DAC through a user processing star and you can implement your user processing in that star. Is it a path you are interested to follow? I would expect 3-5 man days is required in order to do that on our side. If you are interested I can get you in touch with one of our sales agent.


I hope that helps!


Best Regards,
Arnaud

Thanks for the help.


So you are saying that i can change the sampling frequency of the DAC na dmake it equal to the ADC? Or it isn't possible and i have to change it with a processing star?

Dear Sir,


You are trying to feed a ADC output to a DAC. This is fine but this assumes that:


1) The sampling frequency of both ADC and DAC are the same.
2) The resolution is the same.
3) The sample justification is the same.


All the three above are not the case in the standard reference design. Changing the sampling frequency would be about experimenting settings in the clock tree device and I believe you want to place a user processing star between the ADC and the DAC in order to modify the DAC output in a way it can be fed to the DAC (resolution and justification of the samples).


I hope that helps!


Best Regards,
Arnaud