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Timing shift of FMC DAC output

[color=#444444][font=calibri]I am using a development board ML605 with an FMC150 connected to the LPC site. I want to generate two signals, one is output from a DAC of FMC150, the other is output from a GPIO SMA of ML605. These two signals are supposed to begin at the same time, same phase. However, only the initiation timing of the waveform from the DAC of the FMC150 shifts. This shift occurs every time I power on, re-program or does a reset through a push button written in the program, all using the same .bit file.[/font][/color]
Can anybody help me solve this problem?
[/font][/color][color=rgb(68, 68, 68)][font=calibri]Thanks in advance[/font][/color][/size]

This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.
Dear Chao,

I will close this topic in 24 hours unless you provide us some status update.

Best Regards,
Dear Chao,

Are you back on track? Can I go ahead and close this topic?

Best Regards,
I think that is possible, would have to read through the DAC datasheet to see if that is likely, especially where it talks about the elastic buffers.

Overall I don't think I can really help you without spending a lot of time reading carefully through the DAC datasheet, looking at your code or trying a few things on hardware. The best I can do is guess what can cause the problem.  My guess is that it is something digital, either the way the DAC or OSERDES are getting reset and starting up. Or the DAC is not meeting setup and hold times which you would have to add an odelay component. 

Thank you.
Noted, I will check that.
Besides, I checked the clock coming from U4P/N and U2P/N (connected to the ADC on FMC150), they were in-phase when I re-program or does a reset through a push button written in the program.
Is there any possibility that the sampling clock for DAC on FMC150 has the timing shift that I have described below?

I was looking at 088_ml605_fmc150

In the reference design that is what the constraint is set to, probably because that is the sampling rate and that is what the DAC requires for LVDS communication at that sampling rate. I suppose you can set it to whatever you want if you are using a different sampling rate or adjusting it later inside the FPGA. 
Dear Imunoz,

Thank you for your information.

Why the clock coming from U4P/N is 245.76 MHz?
I set the dividing ratio of the output divider 4 to be 8 and the 491.52 MHz was divided by 8.
Then, the output from U4P/N is 61.44 MHz.
Later on, as you mentioned, this clock is input to an MMCM and from the MMCM to the OSERDES.

I used the same clock going to OSERDES to go out the SMA connector.

Dear Chao,

would you have an update on this topic?

best regards,
Dear Chao,
do you have an update on this topic?

Best regards,
For FMC150 I believe the clock coming from U4P/N is 245.76. You can see that in the constraint file where it shows


Why do you think it is 61.44 MHz, have you done modifications to slow the clock? That clock then should go to a PLL and from the PLL to the OSERDES. You should use the same clock going to OSERDES to go out the SMA connector. They should be in phase if you are generating the waveform correctly. Without looking at the code and knowing what modifications you have made it is difficult to say what can be causing random phase shifts.
Dear lmunoz,

Thank you for your information.
As for the vhd files for DAC clock, data, and frame, I used the Xilinx component "OSERDES".
(the clock was input to an MMCM, converted to the single-ended scheme, and input to those OSERDES.)
Besides, I also tried self-made OSERDES.
The timing shift occurs for both of the above cases.
The time resolution of the timing shift is around 2 ns, and its dynamic range is around 150 ns.

One guess that I have is that it is serialization. Are the shifts completely random or they always shifted a multiple of some number?

For example say the ADC takes a sampling clock of 250 MHz and you get a divided version to the FPGA at 62 MHz and you do 4-to-1 serialization. Because it takes 4 cycles of the 250 MHz the same time as 1 cycle of the 62 MHz, it might be randomly aligned in 1 out of 4 positions.

Is the clock you going directly from INPUT BUFFER to a BUFG to a SERDES? I would try an artificial delay on the digital data to see if moving fixes the alignment. For example have a MUX where you can change (while running) if the data going to SERDES gets a delay of 1,2,3,or 4 clocks.

Dear Sir,

Luis will be back to the office next Monday.

Best Regards,
Dear Luis,

Thank you for your reply.

Yes, I want to align a clock out of the SMA connector to a signal coming out of the DAC. I am not using the reference design. Both of those two signals are identical 4-MHz clock. I am not using the 4DSP waveform repeat code.

We had tested our design, and we did not find any suspicious areas that will create that shift. The DAC data bits are in sync with the yellow trigger in our design. The clock that I am using for SERDES is the one coming from U4P/N, which is 61.44 MHz.

If I understand correctly you want to align a clock out of the SMA connector to a signal coming out of the DAC?

Have you completely changed the reference design provided?[size=1em] [/size] What signal are you sending out the DAC and how are you generating it, are you using the 4dsp waveform repeat code? When do you start sending it? What clock are you using on the SERDES the same one going to the SMA connector?