4DSP Products Technical support

As follow up to earlier conversation - [url=http://www.4dsp.nl/forum/index.php/topic,2804.0.html]http://www.4dsp.nl/forum/index.php/topic,2804.0.html[/url], I did attempt to import 156_kc705_FMC150 reference design to Vivado before, without success, as follows:


- generated ISE project in SIP from [font=Verdana]156_kc705_FMC150[/font]
[font=verdana, arial, helvetica, sans-serif]- checked that resulting bitfile is working with fmc15xapp in Ethernet mode[/font]
[font=verdana, arial, helvetica, sans-serif]- imported ISE 14.7 project into Planahead 14.7 , generated bitfile there, tested with fmc15xapp ok (there were several critical warnings about missing definitions for some of the clocking constraints though)[/font]
[font=Verdana]- wrote .xdc file in Planahead[/font]
[font=Verdana]- imported  ISE 14.7 project into Vivado (tried with both v. 2013.4 and 2014.1)[/font]
[font=Verdana]- imported the above .xdc file into Vivado[/font]
[font=verdana, arial, helvetica, sans-serif]- Vivado implementation reports sub-optimal placement for MAC engine and ADC interface clocks error[/font]
[font=verdana, arial, helvetica, sans-serif]- Forcing implementation with CLOCK_DEDICATED_ROUTE fails timing constraints[/font]

[font=verdana, arial, helvetica, sans-serif]Is there a way to fix this problem?[/font]

[font=verdana, arial, helvetica, sans-serif]Here's detailed errors:[/font]

[font=Verdana][/font][code]
[Place 30-150] Sub-optimal placement for an MMCM-BUFG component pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sip_mac_engine_0/mac_engine_inst/brd_clocks_inst/pll0_inst/clkout1] >


sip_mac_engine_0/mac_engine_inst/brd_clocks_inst/pll0_inst/mmcm_adv_inst (MMCME2_ADV.CLKOUT1) is provisionally placed by clockplacer on MMCME2_ADV_X1Y2
sip_mac_engine_0/mac_engine_inst/brd_clocks_inst/pll0_inst/clkout2_buf (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y16


The above error could possibly be related to other connected instances. Following is a list of
all the related clock rules and their respective instances.


Clock Rule: rule_gclkio_mmcm_1load
Status: FAIL
Rule Description: An IOB driving a single MMCM must both be in the same clock region if CLOCK_DEDICATED_ROUTE=BACKBONE
is NOT set
sip_mac_engine_0/mac_engine_inst/brd_clocks_inst/pll0_inst/clkin1_buf (IBUFDS.O) is locked to IOB_X1Y76
and sip_mac_engine_0/mac_engine_inst/brd_clocks_inst/pll0_inst/mmcm_adv_inst (MMCME2_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME2_ADV_X1Y2
ERROR: The above is also an illegal clock rule
Workaround: < set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets sip_mac_engine_0/mac_engine_inst/brd_clocks_inst/pll0_inst/clkin1] >



[/code][font=Verdana][/font][code]
[Place 30-719] Sub-optimal placement for a global clock-capable IO pin-IDELAY-BUFG pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sip_fmc150_0/fmc150_if_inst/ads62p49_phy_inst/I] >


sip_fmc150_0/fmc150_if_inst/ads62p49_phy_inst/iodelay_inst (IDELAYE2.DATAOUT) is locked to IDELAY_X0Y26
and sip_fmc150_0/fmc150_if_inst/ads62p49_phy_inst/bufg_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0






[/code]

Hi Ted


what you can try to do is:
-open a working ISE implemented design in PLANAHEAD and lock the MMCM and BUFG components
-convert these constraints to XDC
-run the VIVADO tool again


Best regards,
Erik

Erik,


Thanks for suggestion. Could you point me towards an efficient way to lock MMCM and BUFG in Planahead and save it in *.xdc? I'm not as familiar with that aspect of the tool (yet) and would be grateful for a bit more help with that now.

Well, I selected Edit->Find->BUFG and checked "Fixed" property for each in Planahead, same for MMCME2_ADV, wrote new .xdc and run implementation in Vivado. New error I get is that BUFG and IDELAY for ads62 are locked to different regions:


[code][Place 30-719] Sub-optimal placement for a global clock-capable IO pin-IDELAY-BUFG pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sip_fmc150_0/fmc150_if_inst/ads62p49_phy_inst/I] >


sip_fmc150_0/fmc150_if_inst/ads62p49_phy_inst/iodelay_inst (IDELAYE2.DATAOUT) is locked to IDELAY_X0Y26
and sip_fmc150_0/fmc150_if_inst/ads62p49_phy_inst/bufg_inst (BUFG.I) is locked to BUFGCTRL_X0Y28
[/code]

Here's perhaps a related issue - Planahead 14.7 does not recognize some of the constraints that SIP generated for ISE, my guess is that it's a syntax issue. Here're the critical warnings it generates:


[code]
[Constraints 18-11] Could not find net '*/SYSCLK_IN' ["C:/FPGA/4dsp/156_kc705_fmc150/output/kc705_fmc150/Src/kc705_fmc150.ucf":158]

[Constraints 18-11] Could not find net 'sip_fmc150_0/fmc150_if_inst/ads62p49_ctrl_inst/clk_div<3>' ["C:/FPGA/4dsp/156_kc705_fmc150/output/kc705_fmc150/Src/kc705_fmc150.ucf":185]
[Constraints 18-11] Could not find net 'sip_fmc150_0/fmc150_if_inst/dac3283_ctrl_inst/clk_div<3>' ["C:/FPGA/4dsp/156_kc705_fmc150/output/kc705_fmc150/Src/kc705_fmc150.ucf":188]
[Constraints 18-11] Could not find net 'sip_fmc150_0/fmc150_if_inst/amc7823_ctrl_inst/clk_div<3>' ["C:/FPGA/4dsp/156_kc705_fmc150/output/kc705_fmc150/Src/kc705_fmc150.ucf":191]




[/code]

Could you tell me what version of ISE tools was used at 4DSP in generation of IP cores for sip_mac_engine part of the reference design? Was it 13.2 by any chance?

[quote author=tedjnsn link=topic=2862.msg15573#msg15573 date=1400265890]
Could you tell me what version of ISE tools was used at 4DSP in generation of IP cores for sip_mac_engine part of the reference design? Was it 13.2 by any chance?
[/quote]


never mind, the info is the IP headers

This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.