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Noise with FMC151

Hello,


I am trying the reference design provided with ML605 and FMC 151. I am generating a 5MHz sine wave with an amplitude of 1V. I am communicating with the board with Ethernet.  I am using the following cable to connect the FMC 151 (MMCX) with a signal generator : http://www.pasternack.com/mmcx-plug-bnc-female-rg174au-cable-assembly-pe36738-48-p.aspx


The waveform obtained with noise is attached with this post. I was wondering if the board would have so much noise in the waveform. I also noticed that the board is becoming much warmer IC. Is this normal?


regards,
Paul





Hi John,

Attached is a new binary file - this one will go through all 32 available tap delays (0 to 31) and save adc0 and adc1 into 32 different txt files.  Please RAR the resulting files with the loopback after you're done.

This allows us to see if there is any value that will result in correct signal.

Tony
Yes.


Log files are identical except that the number of devices is 6 in my log file instead of 3 and the temperature is 29 instead of 39.


Paul
Here is the log file.  Please verify this is the same as what you see on your screen.
Hi Paul,

Attached is the log file that i see when I run the application - you should see the SAME settings (voltage and frequencies) - please verify that this is what you see using the provided application (in the c:\program files\) as well as what i gave you (the list of delays).

I tried the application with the firmware and at tap delay 0, and tap delay 10.  As you can see, tap delay 10 is bad, but tap delay of 0 is good (the default value). 

I'll try to get an applicatio nto you that will create 31 differnet cases in a long loop that will try each tap delay.  You can use Visual Analog as well to verify the results.  IDEALLY though you guy sshould be doing this and setting the tap delays because it's dependent on the board that you're using (trace length, etc. will affect it).




Please find the text files for tap 27:


Paul
Hello,


Please find the text files for tap 22:


Also, note that I changed to a new ML605 board, but of the same type and version .


Paul



Hi Paul,

Thanks for the correction.

Here are two more sets of delays (27 and 22).  Basically the default app has 0 delays and I am trying to figure out if going forward 5 to 10 or back wards -5 to -10 change the received. 

Please let me know which set corresponds with which delay, it'll help the process. 


Second set of text files :



Sorry.


I forgot to do a loop-back and I was monitoring how a square wave would look after the ADC conversion.


I am uploading the loop-back files in these post.


Paul
Actually, both of these sets look like ADC0 has a squarewave.    Are you sure you're looping it back directly???


Hi Paul,

Are you using the loopback cable (DAC to ADC directly with our default firmware) without an external generator?  You'll need to do that for these tests in order to make sense.  The second set (delay 10) looks like there is a squarewave inserted).


Sorry,


I will attach all of delay 5 again.


regards,
Paul
Hi,

The second set is out of range for sure (delay of 10) - i don't see the ADC0 for the first set (delay of 5)  only ADC1.



Paul,

The thing is, in order to rule out the hardware/firmware issue, we need to run with  a predetermined set of known firmware and software.  Namely, our reference software and default firmware.  Your issue looks similar to basically timing related problems on the clock.  In our reference software, you can adjust it here in main.cpp:

case CONSTELLATION_ID_ML605:
    case CONSTELLATION_ID_FMC151_ML605:
        printf("Found ML605 hardware\n\n");
        [b]tapiod_clk = 00; tapiod_data = 0x00;[/b]
        break;

Our hardware/firmware engineers feel that if you return the board, it'll still pass the test we run verifying that te hardware is fine.  The issue with the signal is that we see bit flips (i.e. timing of ADC data coming in to the FPGA).    It's important that the boards (ML605) have similar revisions because some of them will have longer or shorter trace lines from the FMC to the FPGA, that will affect timing delays.

Can you compile the reference software with the reference firmware and try out a few values on tapiod_clk?

Tony
A Second set of text files is uploaded:


Please note that the DAC is connected to ADC0.


regards,
Paul