This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.
almost 8 years ago
Of course this would be possible, typically there is a ZC706 PCIe TRD reference design for ISE 14.6 available from Xilinx, this is a complete linux running on the ZC706 with some host application to test DMA speed I believe. The decision of use Ethernet was to keep interfaces generic across all the platform.
The throughput over PCIe using our core vary depending the carrier and the system. I guess you typically get 500-600MB/s sustained on PC720 (PCIe Gen 2.0, 4 lanes) out of the box. Our PCIe expert is working on an updated PCIe engine where we should get transfers up to 1GB/s on PC720 (Still Gen 2.0 and 4 lanes). This would get much higher on Gen 3.0 or Gen 2.0 8 lanes but we are not yet there.
We have not yet added support for PCIe on ZC706 so you would rely on Xilinx cores and therefor I am unable to provide you with any estimates.
1) Is there any reason why this isn't possible?
2) What is the throughput over PCIe (as achieved on the other carrier boards: ML605, FM680, VP680, PC720)?