4DSP Products Technical support

Hi,

I need to synthesize with the FMC150 a frequency 491.52/3=163.84MHz locked to an external frequency of 10 MHz and I have tried with many configurations and the PLL never locks. I saw that the close loop bandwidth is always very low and this is probably the problem.

How can I increase the closed loop bandwidth?
How do I have to configure the FMC150 to work with an external reference of 10MHz?

One of the tested configurations is:
[font=Arial Narrow]Input reference: 10MHz[/font]
[font=Arial Narrow]Reference divider: 1[/font]
[font=Arial Narrow]M divider: 125[/font]
[font=Arial Narrow]VCO: 491.52MHz[/font]
[font=Arial Narrow]Feedback divider: 48[/font]
[font=Arial Narrow]N divider: 128[/font]
[font=Arial Narrow]Charge pump current: 3mA[/font]

Regards
jv

Hello JV,


I'm sorry for the late reply. Our reference design uses a 100MHz internal reference input. I think testing it with a 100MHz external reference input is a good starting point. In this way, you can use the settings that we made. If it works, then you can change the settings little bit to work with 10MHz external reference input.


Thanks,
Kyu

Hi,

what you propose is what I did. It works properly with the 100MHz external reference but does not lock when the reference is 10MHz.

Regards

JV,


I'm sorry for the late reply. Since 100Mhz input is working, then it is probably the settings that you made for 10MHz input. Could you verify that your M divider and N divier settings are correct? What you can quickly try is to change M divider to 62 or 63 without change any other settings. You can also try it to increase the clock input power. Let me know how it goes.


Thanks,
Kyu

This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.