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Rebuild FMC150 Example SDK Project

I have the FMC150 connected to a Zedboard, and I'm able to run the pre-built binaries. However, I'm not sure how to get my project set up so I can edit the source and rebuild.

I'm used to the PlanAhead workflow, but I couldn't find any ".ppr" project. Since I'm not editing the FPGA code at the moment, I decided to just import the SDK projects and edit software from there.

However, when I open SDK and imported standalone_bsp_0 and zedb_host_if, it seems to be missing the hardware definition file (system.xml).

What do I need to do to set this up?

[code]make -k all
libgen -hw ../sip_zedb_host_if_hw_platform/system.xml\
      -pe ps7_cortexa9_0 \
      -log libgen.log \
Xilinx EDK 14.3 Build EDK_P.40xd
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Command Line: libgen -hw ../sip_zedb_host_if_hw_platform/system.xml -pe
ps7_cortexa9_0 -log libgen.log system.mss

ERROR:EDK:756 - Cannot read XML file ../sip_zedb_host_if_hw_platform/system.xml[/code]

Dear Sir,
That's correct we are not using Planahead flow but ISE instead. StellarIP generates a ISE project (.xise file) which you can open in ISE Navigator. There you have a full project containing the EDK subsystem
Actually the BSP should not be imported but only the software should be imported. This requires:
1) The firmware to be compiled in ISE (Programming files generated)
2) The firmware extracted to SDK from ISE
3) A fresh BSP created in SDK.
4) The host interface SW imported to SDK workspace
5) Change the SW application so it refers to the BSP created in SDK.
I am adding two document. The first one (SD179) is the documentation of the host interface star, You could find that in the firmware source code. Check chapter 6, it is relevant. Typically there is a modification to do in the LWIP stack configuration in the BSP. The second one (UM015) is for another product but the steps in ISE are covered in detail, typically exporting to SDK and creating BSP (chapter 10).
I hope that helps,

Hi Arnaud,

Thanks, that helped a lot. However, the design doesn't meet timing for me.

Here are my basic steps:
[list type=decimal]
[li]Run 4FM GUI Control Application[/li]
[li]Select FW Extractor tab
a) Set Input Firmware Path to "C:\Program Files (x86)\4dsp\Common\Firmware"
b) Set Output folder
c) Click "Install A Specific Firmware" and point to "325_zedb_fmc150.4ff"[/li]
[li]Select StellarIP tab
a) Point to "[outputpath]\325_zedb_fmc150\implement\zedb_fmc150.sdf"
b) Click "Generate"[/li]
[li]Open ISE Project Navigator with"[outputpath]\325_zedb_fmc150\output\zedb_fmc150\zedb_fmc150.xise"
a) Click "Implement Top Module"
b) Wait ~30 minutes
c) Get 3023 warnings and 1 Failing Timing Constraint[/li]
[/list]However, I feel like I'm getting pretty close to getting the SDK project up and running.
I opened the system.xmp from the "Files" section of the ISENavigator project.

Then[size=2] I was able to "Export Hardware Design to SDK...", which appears to have outputted the right files for SDK.[/size]
[size=small]Rather than import the BSP, I did File>New>Board Support Package. However, the generated standalone_bsp_0 seemed to be missing things (lwip, netif, etc) compared to the 4DSP generated BSP.[/size]

I'm running Xilinx 14.4 tools. Win 7 x64.

Hello David,
You are on the right track and your steps are sound, its almost there indeed :)
The timing error you are seeing is a known issue in the sense we have seen then just before the release, this is not crucial as we have tested the reference design for several hours. Note that it is being investigate at the time of writing. It is not crucial as anyway you are likely to change the firmware which will change the routing and implicitly the timings.
In SDK, right click on your BSP in the "Project Explorer" and choose "Board Support Package Settings". Inside the dialog you should tick the "lwip140" component, this will add the Xilinx TCP/IP stack inside your BSP and then it should work better. As soon the checkbox is ticked you will see on the overview in the left side of the dialog is a lwipxxx you can click on. Inside there, expand the "tcp_options" and change "tcp_snd_buf" from 8192 to 65535 as per SD179, quote from SD179:
[quote][size=3]The Xilinx SDK BSP should be modified to include LWIP stack and the tcp options should be changed in order to have a 65535 bytes wide ‘tcp_snd_buf’ in the LWIP stack configuration.
Also, the code providing Ethernet in a single execution context. The TCP/IP stack is calling a callback function each time a packet is received. There is not much room for something else unless there is a multithreading environment. The only way to achieve that is to run Linux on the Zynq board. We have recently released a ZC702-FMC150 linux package where Linux boots on ZC702 and one can call FMC150App from Linux.
Best Regards,
Thanks for the help; I somehow missed that line (even though it was bright red).
I can build the software now.

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