The FMC150 reference design for the KC705 Kintex-7 board seems to accommodate burst modes only for the ADC and DAC. I need to operate them continuously. Is there a way to command Stellar-IP to return continuous samples from the ADC, synchronized to the ADC clock, without the need to re-trigger? Is there a way to provide continuous samples to the DAC, synchronized to the DAC clock, without needing to re-trigger it either?
I appreciate your replies. They're very helpful, but it's good sometimes just to know somebody's out there listening.
I have been closely studying your reference design. I already considered redoing the data buffering in the FMC150 star, but the FMC150 emulator in the simulation model confuses me a bit. ADC samples are represented by the output of a pseudorandom number generator, where one random bit is mapped to all the even or all the odd bits of each sample. I'm not certain I'm reassembling the sample bits correctly.
It would help if you could confirm which signals in the reference model simulation represent the raw, unbuffered ADC samples. I can take it from there.
I appreciate your additional pointers, and all those factors are part of my ongoing design.
over 8 years ago
Hello Kevin, The ADC is continuously acquiring data, the data buffering in the FPGA should be rewritten. I think you will need to simulate/understand the reference design and you will then have a better insight on how to modify the reference design in consequence. This request is really outside the scope of technical support, you can decide to adapt our reference design (which is provided as source code, free of charge) or to contract us to take care of your integration issues, your decision. I will give you a few pointers but I cannot do more: 1) What is the bandwidth of the stellarIP data bus connecting A/D and D/A, would this bus be sufficient in term of bandwidth? 2) Do you need external memory for your processing where the reference design only use a 64kB FIFO? 3) Is the fabric running fast enough for you to stream/process all this data? 4) What actual sampling frequency you target as this dictates the data flow? 5) In the reference design , samples are extended to 16 bit, maybe this is not sufficient for your application? I hope that helps, Arnaud
over 8 years ago
Thanks for the reply. I'm afraid I wasn't very precise in describing what I need. I don't need continuous samples returned to the host PC. I need continuous samples from the ADC to feed to on-chip signal processing and then to the DAC. After initialization, it will operate without involving the host computer.
How can I obtain a continuous stream of ADC samples and their associated clock [i]within the FPGA only[/i]?
How can I provide a continuous stream of samples to the DAC, synchronized to the DAC clock, [i]within the FPGA only?
over 8 years ago
Hello Kevin, That's correct, our reference design is using a TCP/IP less communication protocol which is not suited to be reliable and with high transfer speed. Generally the best you will get is a few MB per seconds. Generally our customers in the need of streaming are purchasing a PCIe enabled design where they can get a decent transfer speed, suited for streaming. Note that to stream DAC/ADC you will need more bandwidth than what is actually available on the PCIe. Even having the PCIe engine instead the Mac engine will not provide you with a streaming solution as the buffering will be done on the DDR3 memory rather than on the BRAM FIFO used in our reference design. The best approach here would be to contact my sales colleagues and define what you need. Then we will be able to offer you with a solution able to fullfil your requirements. Best Regards, Arnaud