[font=calibri, sans-serif][size=15px]Now After receiving the FMC150 as part of the kintex7dsp kit for a moment I have begun a study of using it. May I have some questions as below?[/size][/font] [font=calibri, sans-serif][size=15px] [/size][/font] [font=calibri, sans-serif][size=15px]1) I note from k7dsp_rtl_tutorial's configuration-related files that the 'ext'[/size][/font] [font=calibri, sans-serif][size=15px]clocking option means the ext clock from the mmcx connector is feed directly to the o/p dividers. If I want to use the ext clock as the (sec) reference to the PLL (I will need to change the s/w configuration setting), is it supported already by the h/w without any modification? In other words, please clarify "assembly option" stated in Fig. 5 of the user manual.[/size][/font] [font=calibri, sans-serif][size=15px] [/size][/font] [font=calibri, sans-serif][size=15px]2) The user manual states about External Clock/Reference Input that "input[/size][/font] [font=calibri, sans-serif][size=15px]level: 0.1 – 1.3 Vp-p; 50 ohms; (AC coupled)". Can it be a sinusoid at 0.5 Vpp (i.e., -2.04 dBm)?[/size][/font] [font=calibri, sans-serif][size=15px] [/size][/font] [font=calibri, sans-serif][size=15px]3) How to bypass the DAC re-construction filters [/size][/font][size=15px][font=Calibri]with 0-ohm resistors according to the user manual?[/font][/size]
[font=calibri, sans-serif][size=15px]4) Is it possible to use the OSTRP port of the DAC?[/size][/font]
Customer
[font=calibri, sans-serif][size=15px]Now After receiving the FMC150 as part of the kintex7dsp kit for a moment I have begun a study of using it. May I have some questions as below?[/size][/font]
[font=calibri, sans-serif][size=15px] [/size][/font]
[font=calibri, sans-serif][size=15px]1) I note from k7dsp_rtl_tutorial's configuration-related files that the 'ext'[/size][/font]
[font=calibri, sans-serif][size=15px]clocking option means the ext clock from the mmcx connector is feed directly to the o/p dividers. If I want to use the ext clock as the (sec) reference to the PLL (I will need to change the s/w configuration setting), is it supported already by the h/w without any modification? In other words, please clarify "assembly option" stated in Fig. 5 of the user manual.[/size][/font]
[font=calibri, sans-serif][size=15px] [/size][/font]
[font=calibri, sans-serif][size=15px]2) The user manual states about External Clock/Reference Input that "input[/size][/font]
[font=calibri, sans-serif][size=15px]level: 0.1 – 1.3 Vp-p; 50 ohms; (AC coupled)". Can it be a sinusoid at 0.5 Vpp (i.e., -2.04 dBm)?[/size][/font]
[font=calibri, sans-serif][size=15px] [/size][/font]
[font=calibri, sans-serif][size=15px]3) How to bypass the DAC re-construction filters [/size][/font][size=15px][font=Calibri]with 0-ohm resistors according to the user manual?[/font][/size]
[font=calibri, sans-serif][size=15px]4) Is it possible to use the OSTRP port of the DAC?[/size][/font]
[font=calibri, sans-serif][size=15px]Thanks,[/size][/font]
[font=calibri, sans-serif][size=15px]Tanee[/size][/font]