I have one problem with CDCE72010. I am setting divider's M=625, N=384, P=8, R=1 i.e. Register10 = 05FC270A, Register11 = 0000040B. Now if I am changing M value to 624 or N value to 385 i.e. Register10 = 05FC26FA or Register10 = 0600270A then PLL of CDCE is not locking..........why ? What is the range of VCO ? Because i want to generate 512 MHz from VCO so that i can get exact 32 MHz frequency at output.........what should be the probable solution ? [color=#888888] santosh[/color]
The CEDE72010 uses an external VCO. I assume you are working with a standard FMC150 configuration, in which the VCO has a frequency of 491.52MHz with a typical Kv of 445ppm/V. A frequency of 512MHz is out of its range. You could used an external clock or contact [email]firstname.lastname@example.org[/email] for a custom VCO option.
over 8 years ago
Since last month I am doing alot of experiment on harware and I am using Avnet's reference design, I have noted two points while verifying it on hardware,
(1) If I am providing external loop back i.e. from DAC to ADC, then at the output of DDC we should get a perfect sinusoid, But I am not able to get it, and I have checked output of DAC on oscilloscope that is a perfect sinusoid, Why it is so ? and I have followed all the steps correctly. Now, If I am providing single channel feedback then at the output of DDC I am getting perfect sinusoid on both the channel,,,,,,,,Why.....?
(2) Now if I am giving 10 MHz external signal from signal generator to the ADC and I have bypassed it directly to the DAC ,So it should give same signal at the output But it is not happening, Why ? (sampling rate of ADC is 61.44 MHz ) and f I am giving 30.72 MHz external signal from signal generator to the ADC then it is showing me appox. same signal,,,,,,,,,,I am not getting that Why ? it is happening.
over 8 years ago
we're not aware of the specificities of the Avnet reference design and I advise you contact Avnet in that regard.