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PSK radio link and clock (coherency)


I try to do a PSK radio link but i'm a bit lost howto do a clock recovery on receiver with FMC30RF. Does someone got any informations about this kind of usage ? How can i do a PLL lock on receiver about transmitter ?

Thank you.


The FMC30RF does not implement a PSK demodulator. The demodulator chip on the FMC30RF, the TRF371125 is a I/Q demodulator which means that it performs down conversion, and generates a complex output from the spectral input. There is no hardware feed-back that allows you to adapt the ADC sample clock (nor the LO) to the received PSK signal. You will have to perform your clock recovery in the digital domain, using DSP software or DSP inside the FPGA.

Best regards,
Ingmar van Klink
Dear Sir,

Have we informed you sufficiently, can we go ahead and close this topic?

Best Regards,

First thank you for your fast answer.

Do you have any exemple how to do numeric processing ?

I have my own code but it's not perfect (10 -4 error rate) and I cannot apply any correction code due to time limit.

Another question, do you know how to bypass fifo in texas receiver component ?

Thank you.

We don't have an example to perform the numeric processing of your PSK signal.

For bypassing the FIFO, please go to section 5.1 of the datasheet.

Best regards,
Thank you
This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.