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Continuous ADC reading, sample rate


we have two questions regarding the board.

From the documentation of the firmware (SD111 FMC30RF Star) I can see that the user is capable of setting the burst size and the number of bursts that should be captured. If I understand it correctly, I have to set a trigger for each burst individually, even if I define multiple bursts to be read. However, for our application we need a continuous stream of samples from the ADC. I wonder how we have to control the component in order to manage that. We will connect the output FIFO to a PCIe core that is capable to handle the data rate, so we read data from the FIFO whenever it becomes available. If we have to set the trigger for each burst individually, when do we have to do that for continuous mode of operation? Or maybe we have to bypass the trigger logic
in VHDL and write each sample into the FIFO?

And we have another question: In Figure 1 of SD111 it is written that the ADC clock is 368.64 MHz. With DDR transmission on 2 wires that allows to transfer only 122,88 Msps. I wonder whether this number is correct or the number of samples given on the website and the introduction is correct (125 Msps). It's important for us to know the exact sample rate.

Thank you!

This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.
Dear Arnaud,

feel free to go ahead with closing the issue.

Best regards,

Dear Sir,

I will close this topic in 24 hours unless you have an objection.

Best Regards,
Dear Sir,

Let me know if I have informed you sufficiently, if so I would like to close this topic.

Feel free to open any new support topic if you need to do so.

Best Regards,
Thank you for the prompt reply!
Dear Sir,

As far as the first question is concerned, by looking at the firmware source code you will be able to modify the reference source code to have an "continuous" acquisition mode, you send a trigger and you get nsamples * nbursts in the FIFO. This is not implemented so you will need to implement that on your side; SDs, CDs and source code should have enough information so you can carry this task on.

About the second one, in the reference design we set the clock to 122.88MHz, yielding into a 368.64MHz.

I hope that helps,