Can you share any details regarding the on-board reference clock on this card? Can you provide the part number? Is it just a 30.72 MHz crystal oscillator or something that is programmable/configurable? Thanks.
Edit: Also, when I run the demo application, I get an ADC PHY clock at 307.21 MHz, a DAC PHY at 307.19 MHz, and a CDCE62005 Spare at 614.4 MHz. The SD111 FMC30RF Star documentation shows that the ADC/DAC PHY clocks should be 368.64 MHz? And the post on this board on the reference design details suggests that the output from the CDCE60025 to the FPGA should be 245.76 MHz? Can you help shed some light on this situation?
I have checked both reference designs and the clocking scheme is different. On the Zedboard-FMC30RF design (Avnet reference design), everything is clocked on FCLK0 which is set to 50MHz. In the 4DSP reference design everything is clocked on FCLK2 which is set to 125MHz.
So you can either modify the software, in order to use 50MHz for you calculation because this is what you have right now or modify FCLK0 to be 125MHz and then re export the design to SDK so you get an updated ps7_init.tcl file. The booting of the Arm, including setting PLLs is done by this tcl file. In your case you changed FCLK0 to 125MHz but you have not exported to SDK, so you were still using the old ps7_init.tcl setting up FCLK0 to 50MHz, I guess it now makes sense. Everything works fine on 50MHz besides the frequency display, actually the Avnet reference design only comes with a GUI to display spectrum and this is why this problem was not spotted earlier.
Best Regards, Arnaud
over 7 years ago
This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.