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Clock questions for fmc30rf_if.vhd

4DSP support:

    There are several clocks in fmc30rf_if.vhd and these are ones I would like to understand better:

    1) Please specify the clock rates for these and what is the purpose that these clocks serve. 
    2) Which clock is the main fpga clock? [ Is it clk?]
    3) What is the purpose of clk_cmd?
    4) What is the purpose of clk_to_fpga_buf?


1) clk = clk_cmd = 125MHz
    tx_clk = rx_clk = 122.88MHz
    clk_to_fpga_buf = 245.76MHz
2) Clk and clk_cmd are the same in the firmware. clk_cmd is the main clock that are used to syncronize with the StellarIP interface. tx_clk and rx_clk are used for tx and rx operations. 
3) clk_cmd is the clock synchronized with 4DSP StellarIP interface.
4) This is an auxiliary clock. Currently, it's not used. You can change the clock frequency by setting the clock tree device with your configurations.

Thanks Kyu:

    A few more questions:

    1) Why is the ADC/DAC clock [122.88MHz] slower than the FPGA clock[125 MHz]?  Especially when the A/D is supposed to be 125 MSPS.
    2) Why is the ADC and DAC clock the same when the DAC is supposed to be 250 MSPS?
    3) What is the [b]Spurious-Free Dynamic Range[/b] ([b]SFDR[/b]) of the Transmit and Receive side supposed to be? Shouldn't it be 72 dB 12 bits * 6dB per bit?
    4) Are there schematics available?

1) FMC125 MHz is the clk_cmd that is synchronized with 4DSP StellarIP interface. It's not dealt with ADC/DAC clocks. The reason why it uses 122.88Mhz is that actual ADC_DCLK and DAC_DCLK are 368.64Mhz which is generated from the multiple of the reference clock input 30.72MHz. Then it goes through the serdes with 368.64Mhz and 122.88Mhz.
2) DAC uses an interpolation by 2.
3) That should be the theoretical SNR. The board is characterized by TI and TI has not finalized the report yet. The report will be available next couple of weeks.
4) I'm sorry that we do not support schematic. Please, contact the sales.

Please, refer the source codes, datasheets and 4DSP documents.

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