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FMC150 to KC705 rev.C

I am using a KC705 Rev.C board and a FMC150 r2.1

The stellarIP software couldn't generate the 156_kc705_fmc150.dsn saying that it couldn't find the .xdc files when I tried to generate under Vivado terms, and when I tried to generate to ISE I get the message "Unknown property value "xc7k325t" while executing "project set device xc7k325t"". The license also stopped working after a day.

Using the KC705 fmc150 reference design I was able to program my board but both DAC's only output a sine wave with no reference to the wave I put into the ADCs. How do I get the board to take in a wave from a waveform generator and have it output to the DAC?

Is there a reference design which also includes a microblaze along with the FMC functionality?


Constellation 156 doesn't support Vivado yet. Did you enable Vivado flow support in Design Details (Ctrl+D) in StellarIP yourself? By default it should not be enabled. Could you please try to run generate with a clean .dsn taken from the BSP release with ISE support.

The reference design supports acquisition of data on the ADC inputs, and generation of a waveform on the DAC outputs. These two are not linked, is there a specific reason that you want to replay the ADC waveform directly on the DAC outputs? In the reference software, Fmc15xAPP -> main.cpp, you will see that the software generates a waveform that is loaded to the DACs (function: GenerateWaveform16()). By modifying this function you can change the output waveforms of the DACs.

We don't have a reference design that includes microblaze support, if you want to have such a reference design I would recommend you to get in contact with the sales department.

Best regards,


We already performed your suggestions about running a generate only with ISE, however we get an error saying that "Unknown property value "xc7k325t" while executing "project set device xc7k325t"".  Is there any way to fix this so we can generate for ISE?

Also the license also stopped working after a day, is there a reason for this?

We understand the reference design does not support ADC inputs, we were wondering how we would enable ADC inputs. We want the microblaze to read in the ADC values and then put these values out into the DAC. Is there any suggestions you can give us?

Could you provide/confirm the version of StellarIP and ISE that you are using?

The license shouldn't stop, I will discuss this internally.

Do you want to read the ADC and forward to DAC in the microblaze in real-time? Or do you mean snapshots of samples?

Best regards
We are using ISE 17.7, and Stellar IP is version

We want to read from the ADC in real time and put the data into the microblaze then output the microblaze data to the DAC.

Do you mean ISE 14.7? What kind of ISE license do you have? According to , the Webpack license doens't support the xc7k325t.

I wouldn't recommend to use the microblaze for real-time processing, unless you are using ADC/DAC sample clocks in order of 1 to 50MHz, it is highly unlikely that the processor will cope with these datarates. Instead you should just use VHDL to implement this.


We are investigating your StellarIP licensing. Could you send the file:
C:\Program Files (x86)\4dsp\4FM Core Development Kit\Bins\Log\AutoUpdate.log to , please add a line with the link of this forum topic in the mail.

We have some VHDL code that your website provides that produces its own sine wave from the FMC card and output this sine wave to the DAC. We however are unable to get the ADC to read in an input, how do we do this?
Here is some of the code from out project. Are the cha_p and cha_n std_logic_vectors the ADC_in ports? These aren't connected to anything, as far as we can see looking at this code.
The project name from your website: kc705_fmc150_ILA3.VHD

--Clock/Data connection to ADC on FMC150 (ADS62P49)
  clk_ab_p        : in    std_logic;
  clk_ab_n        : in    std_logic;
  cha_p            : in    std_logic_vector(6 downto 0);
  cha_n            : in    std_logic_vector(6 downto 0);
  chb_p            : in    std_logic_vector(6 downto 0);
  chb_n            : in    std_logic_vector(6 downto 0);

  --Clock/Data connection to DAC on FMC150 (DAC3283)
  dac_dclk_p      : out  std_logic;
  dac_dclk_n      : out  std_logic;
  dac_data_p      : out  std_logic_vector(7 downto 0);
  dac_data_n      : out  std_logic_vector(7 downto 0);
  dac_frame_p      : out  std_logic;
  dac_frame_n      : out  std_logic;
  txenable        : out  std_logic;

The reference design is the correct design to use. This is the design that you tried to use initially. The VHDL file you are referring to is not part of this design, did you get it from Avnet?
If you take the .bit file that comes along with the 4DSP BSP and use the Fmc15xAPP.exe you will be able to acquire samples with the ADC. This .bit file generated from the original 156_kc705_fmc150 StellarIP project. If you are not familiar with StellarIP I would like to point you to the 4FM Getting Started Guide document.

Is your StellarIP working? I think we didn't receive the autoupdate.log did we?

Best regards

This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.