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Changing the ADAC Sampling Clock in the ML605 Reference Design

We are having all sorts of fun with the reference design. It performs pretty well. But now it is time to increase the sample rate so we can operate with our intended IF. Does 4DSP have any tips or application notes so we can benefit from the design team's knowledge of the FMC150?

Hello John,

Happy to hear the reference design suited your needs up to now. We do not have much guidelines. Increasing the sample rate might cause timing issues which would need to be asserted by the designer.

Best Regards,


Yes, I can see that there is little in way of guidelines on the 4DSP Website. I understand that changing the clock rates of the FMC150 devices will impact the FPGA design. I guess what I was looking for is some insight the FMC design team might have regarding the expected performance of the FMC-150 and any know pitfalls we should avoid during our development.

I would very much like to see the same. I have an immediate, specific application requiring a sample rate of approx. 250Ms/s (yes, 245.76 is adequate) on the A/D and the D/A.

First test is a simple loopback from a modulator through the DAC, through the MMCX cables, back through the ADC, and through the demodulator.
Dear Avnet users,

Maybe formulate questions and precise requests and I will see what I can do.

Best Regards,

OK, Arnaud -- here is my precise request:

Using Simulink - HDL Coder, I have created an FPGA-in-the-Loop model in which my baseband modulator, simple channel simulator, and baseband demodulator are on the ML605 board, and my system top level, video source extractor, and video display driver are on the host computer. My nominal chip clock rate for my channel model is 250Ms/s. Communication between the ML605 and the host computer is via a GigE cable, with the MAC layer coded by Simulink's tool.

I am attempting to insert an analog loopback, in which my (quadrature) modulator drives the FMC150 DAC(s), whose analog output(s) are wired back to the same FMC150 ADC's input(s). In turn, the ADC's digital outputs would drive the FPGA-based demodulator.

I have been attempting to merge the DUC/DDC demo model into mine, but I am getting a very unhelpful "hardware did not return information" error message from Simulink, meaning that the Ethernet MAC did not receive a response on time. I strongly suspect something is amiss in my clock tree structure, but I am open to other suggestions, as well.

To get my original model running, before I added the FMC150 board, I had to hack the machine-generated VHDL code a bit to tell it that I had a channel clock which was faster than the Ethernet MAC clock. I did this by editing the MMCM to slow down the MAC clock to (200MHz*5)/128, so that I could run my chip/channel clock at 200*5/4 = 250MHz. I need to decide whether to run my design on the FMC150's clk_ab and figure out how to speed this up by a factor of 4 (I am not using the demo's DUC/DDC/DDS) or to figure out how to slave the FMC150 to my 250MHz clock, which of course I can slow a little if 246Ms/s is a hard limit for reliable operation.

Thank you for any insight you can provide.
If possible , Please share information with me
I'm also trying to change the sampling clock to 250Msps.
I'm testing the ML605 Board with the FMC board.

If you agree with me, I will share my result with you.

I'm changing the memory initializing file, "ads62p49_init.coe" and "cdce72010_init_int_491_52MHz.coe".
that files contain some valuable information about the ADC and the Clock chip.

Name :  Ki-hyun,kim
email :  [email][/email]

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