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Configuring the front panel clock input as the A/D sampling clock

The kit came with source code in a reference design.

The top level file is

The document for the kit does not explain how the reference design works.  I had a question concerning the configuration of the FMC150.

I want to configure the FMC150 so that the  is the sampling clock.

  In ml605_fmc150.vhd, there is an input that is controlled by a switch on the motherboard:

Line 1280:

external_clock <= gpio_dip_sw(2);

Will this switch input result in changing the A/D sampling clock to the clock input on the front panel of the FMC150?

If this is not the case, can you explain how I would change the configuration to set the A/D sampling clock to the front panel clock?

You may indeed change the state of the DIP switch to switch from internal clock to external clock.
After, you need to reload the firmware, or press the CPU RST button (SW10) on the ML605.

Kind Regards,
Thanks Peter.
The Avnet kit has a getting started document: GS-AES-V6DSP2-LX240T-G-12_4.pdf.  But this doesn't have any details for the reference design.
Is there a 4DSP document for this reference design?  I have been slowly trying to understand te design by reading through the source code and writing down notes.

Avnet might have additional documentation, not sure about that.

Best Regards,

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