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FMC204 DAC clocking


I want to use all the four DAC channels in FMC204. For this, I made a very simple code which sends the same signal from a VC707 memory signal to all the channels.

I am using ODDR in FPGA to send data to the converters. The clock is an external 2GHz, that is being divided by AD9517 (in FMC204) to generate a 125 MHz clock which is sent to DACs and FPGA. I am clocking both ODDR within the FPGA and DACs CLKIN input with this 125 MHz clock

I am configuring all the register in FMC204 (CPLD, PLL, DACs). However, the signal on the oscilloscope is all messed up.

I think the problem can be with the clock configuration, because DAC5682z is not clear about the clocking. However I tried many things and none of them worked.

Does anybody know the proper way to configure this board for DACs operating in dual channel at 125 MHz?

Thank you in advance
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