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Timing Errors in FMC216 Vivado Reference Design

Hello,


I just tried to generate a .bit file with Vivado out of the 527_vc707_fmc216 reference design, which was created by StellarIP and which was successful but with timing errors:


[Vivado 12-1387] No valid object(s) found for set_false_path constraint with option '-to [get_clocks mmcm_adv_inst_n_6]'. ["C:/StellarIP_Project/Extracted/527_vc707_fmc216/output/vc707_fmc216_vivado/Src/vc707_fmc216_vivado.xdc":193]
[Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.


[Vivado 12-1411] Cannot set LOC property of ports, Site location is not valid ["C:/StellarIP_Project/Extracted/527_vc707_fmc216/output/vc707_fmc216_vivado/Src/vc707_fmc216_vivado.xdc":157]
[Designutils 20-964] Command failed: . ["C:/StellarIP_Project/Extracted/527_vc707_fmc216/output/vc707_fmc216_vivado/Src/vc707_fmc216_vivado.xdc":157]
[Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.


With Vivado Version 2015.2 I've got a Worst negative slack of -7.6ns and a Worst Hold Slack of -1.5ns.

With Vivado 2016.2 I've just got a Worst Hold Slack of -1.3ns, which is still not acceptable.

When I look at the timing summary I get some more information where the errors occur:
Clock: sip_fmc216_8lane_0/fmc216_0/xcvr_wrapper_inst0/xcvr_fmc216_init_i/U0/xcvr_fmc216_init_i/xcvr_fmc216_i/gt0_xcvr_fmc216_i/gtxe2_i/TXOUTCLK


From Clock: clk125mhz

To Clock: sip_fmc216_8lane_0/fmc216_0/xcvr_wrapper_inst0/xcvr_fmc216_init_i/U0/xcvr_fmc216_init_i/xcvr_fmc216_i/gt0_xcvr_fmc216_i/gtxe2_i/TXOUTCLK


From Clock: sip_fmc216_8lane_0/fmc216_0/xcvr_wrapper_inst0/xcvr_fmc216_init_i/U0/xcvr_fmc216_init_i/xcvr_fmc216_i/gt0_xcvr_fmc216_i/gtxe2_i/TXOUTCLK

To Clock: clk125mhz

Which Version was used during development and do you have any idea how to get rid of these timing issues?

Thank you so much and best regards
Jan-Philip

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