The Vivado version used to release the firmware you have was 2015.1 . Due to different routing seed an routing methods of the tool, the design did not show any timing error in Vivado 2015.1.
The failing timing paths are completely asynchronous clock domains, and the firmware implements proper clock boundary crossing logic where necessary. Therefore you can set false path constraints between clk125mhz and fmc110_clk_div32 and div16, for example add the line below to your .xdc:
set_false_path -from [get_clocks clk125mhz] -to [get_clocks fmc110_clk_div16]
Ingmar van Klink
Thanks for your reply. I have opened a new ticket and my problem is solved as in the link below:
Hello, we recently bought FMC110 Card to use with VC707 and Vivado. After I made the synthesis and implementation with Vivado 2017.4, I got the critical warnings for timing violations. I showed them in attached files. Are they important ? Is there a way to remove them completely ? Maybe you have specific implementation or synthesis settings for Vivado that I should apply ?
There is someone else asked for the similar problem in the link below, but his question seems not responded. Hopefully mine will be responded :) Thanks.