There’s a potential issue in FMC160, FMC161, and FMC163 ADC pin training when sampling approximately between 1200-1400 MSPS per ADC, which is different than the default sampling frequency for any of these BSPs. When this issue has been discovered in any of these BSPs, removing at least one of the two ADC clock adjustment phases in pin training has resulted in a working solution.

FMC160 Example

Here is the solution that was implemented on the FMC160 star included in Constellation ID 735 (VP881 + FMC160):

Remove the following pieces of ADC pin training…

•    Phase 1: clk_alignment

This initial phase is similar to the calibrate_bit in phase 2, but it increments clock delays (the delay_value signal passed into clk_idelay_set) while checking for pattern matches on the master bit. This functionality is implemented in digital logic that is clocked by the very clock that it is attempting to change.

•    Phase 1 helper: bit_read_end

This module is used by clk_alignment. It is similar to bit_read used by phases 2 and 4, but it starts at index 1 and searches through the clock delay values vector for master bit pattern matches.

•    Phase 3: calibrate_clk_adj

This phase takes in the clock delay value from phase 1 and the master bit delay value from phase 2 and attempts to adjust both of these delays to place them in the middle value of the master bits delays. This module's output is added to both of the phase 1 and phase 2 (clk and master bit, respectively) initial results for another adjustment to both in this phase.

•    Phase 1 and phase 3 helper: clk_idelay_set

This module is used to compare the current clock delay against the desired clock delay and changes the clock if needed. In UltraScale, this is really phase shifting MMCM clock outputs.

Keep / modify the following pieces of ADC pin training…

•    Phase 2: calibrate_bit

This is now the first phase and is used to place master bit in the middle of the widest data eye.

•    Phase 3: calibrate

This is now the second phase and is used to place all other bits in the middle of the master bit's selected data eye.

Source Code Changes

The changes described above have been attached to this post for reference. There are 3 VHDL files that are modified to implement the above changes and they're all included as _old and _new for comparison.