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FMC125 "Apply sync (through CPLD)" clarification

In fmc12x_adc.cpp, line 107, there is the following code:

// Apply sync (through CPLD)
rc = sipif_readsipreg(bar_cpld, &dword);
return rc;
dword &= ~0x10;
rc = sipif_writesipreg(bar_cpld, dword); Sleep(10);
return rc;
dword |= 0x10;
rc = sipif_writesipreg(bar_cpld, dword); Sleep(10);
return rc;[/code]

I believe this doing a read-modify-write to the CPLD (via SPI via I[sup]2[/sup]C).  I see that it reads 0x18, then writes 0x08, then writes 0x18.  However, from reading the FMC12x User Manual, the CPLD register only selects the SYNC source, but does not actually assert SYNC.  Specifically, it reads that SYNCSRC is No Sync, then sets it to Carrier (trough [sic] SYNC_FROM_FPGA_P/N), then sets it back to No Sync.

If my understanding is correct, this appears to be a bug because SYNC is never asserted.  Anyhow, I would appreciate clarification on the matter.

Dear Sir,

On many xilinx carrier, the SYNC signal is not routed to the FMC connector. We have this workaround (not necessary if you are using 4DSP carriers) in place. The idea is that SYNC_FROM_FPGA are pulled up on the mezzanine board.

The software changes from '0' to SYNC_FROM_FPGA (pulled to '1' by pull up) and back to '0'. If you look at FMC12x user manual chapter 4.5 you will see that the LVDS mux directly connects to ADC SYNC. Switching '0' to '1' and then to '0' causes a SYNC pulse on the ADC.

I hope that helps,

Thanks, that does clear things up.

I think it would help avoid confusion if the reference design for the ML605 did not have sync_from_fpga pins in the top-level VHDL and UCF.  Also, I think it would help if the pull-ups were shown and/or explained in the FMC12x User Manual.
Dear Arnaud,

I'm facing that issue at the moment. Could you please clarify the following issues?

I am trying both, a) SYNC pulse from FPGA through SYNC_FROM_FPGA and b) external SYNC pulse (as we will need to synchronize multiple ADCs later on). I am sending the same (sinusoidal) signal to the 4 channels of the FMC125 hosted on a ML605.

1. Even with 4dsp .bit and C files ("Apply sync through CPLD") I see that the outputs are not synchronized (moreover, the delays/latencies are NOT deterministic ), actually it gives the same result as NOT sending the SYNC pulse.

2. With a external SYNC pulse (commenting the "Apply sync through CPLD" part on C code), I see the same issue as before i.e. outputs NOT aligned and not deterministic delays

3. Different from what you said, I can see that SYNC signal IS routed on the ML605 (according to the datasheet). Could you confirm that the following code generates a pulse through SYNC_FROM_FPGA (sometimes does not work)

rc = sipif_writesipreg(bar_adc_phy+0, 0x80); Sleep(10);

4. In the app. note "EV10AQ190A Synchronisation" from e2V, figure 1-3 shows a correct SYNC pulse timing, does this apply to EV8AQ160 as well?

Hello Daniel,

1. The reference design from 4DSP does not synchronize the four channels. The reference design only supports sequentially grab a snapshot from each channel.

2. Same comment as 1.

3. The ML605 implements a uni-directional buffer and only supports a direction from FMC to FPGA. The SYNC signal needs direction from FPGA to FMC. It is therefore not possible to drive the SYNC signal from the FPGA on the ML605.

4. Yes.

Best Regards,
This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.