I'm using an FMC125 on a ML605 and somewhere around every 1000 or so SPI reads, the SPI read hangs. I've tracked this problem back to [font=Verdana]the Wishbone I2C Master arbitration lost (al or i2c_al) signal is asserted during SPI reads over I2C using ChipScope. [/font]
Specifically, fmc125_sc18is602b_ctrl tries to initiate an I2C access for the SPI read. The go signal is asserted in i2c_master_byte_ctrl, but al is asserted as well, causing i2c_master_byte_ctrl to remain in the st_idle state instead of proceeding to st_write as it normally should. fmc125_sc18is602b_ctrl gets stuck in the wait_irq_l (which I think should be named wait_irq_1, since it's waiting for wb_inta = '1') waiting for an interrupt that will never happen b/c the i2c_master_byte_ctrl never went from st_idle to st_write.
Since there are no other I2C masters (except the other I2C master in fmc125_if, which is idle since there are no register accesses causing it to generate an I2C transaction) active, arbitration lost should never be asserted. I believe the problem is that the pull-up is too weak. I tried adding the FPGA pull-up register, but the problem still occurs.
What is the strength of the pull-up resistor that you expect on the I2C lines? I want to check that it is what is actually on the board. Also, if there are any other ideas on why this is happening, I would appreciate it.
I worked around this issue by slowing the I[sup]2[/sup]C frequency by half, by setting the prer register to double the value.
While I do have a work-around, I think there is an actual underlying problem. The I[sup]2[/sup]C bus is supposed to be working in Fast-mode, but do not satisfy the t[sub]r [/sub](rise time of both SDA and SCL signals) max of 300 ns specified in the UM10204 I[sup]2[/sup]C-bus specification and user manual Rev. 5 pg. 48.
about 5 years ago
We are using 100kHz i2c reliably in our reference design, we have not used/tested 400kHz i2c.