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constellation generation issues (ML605 with FMC126)

Hello,

for few days I try to implement a contellation based on FMC126 firmware. I used all stars presente in the ML605_fmc126 firmware and I added one.
During the generating step I have got an error that I don't understand.
In the debug window I have this message :

[b][i]INFO : Could not find ucf fragment for 'sip_data_processing' ID=0 (C:\...\star_lib\sip_data_processing\sip_files\sip_data_processing_ML605_0.ucf)[/i][/b]

I changed the .ucf file name for sip_data_processing_ML605_0, checked if the file is in the right folder and relaunched the generation but the error still here.

The problem could be something else but I don't know where.

all the Best,
Alexandre.

Dear Alexandre,


The only thing I find odd is the C:\...\, did you shorten that on purpose?


Could you detail more about the actual folder hierarchy such as do you have the same architecture as the initial constellation?


If you wish you can create an archive of your project ( without the output folder ) and send it to support@4dsp.com. I will surely have a look at it.


Best Regards,
Arnaud
Dear Arnaud,

first thanks for reply. Actualy yes, I shortened the folder path. It seemed to me not an important point, but I should have mentioned it. The complete error mesage is the following :

[b][i]INFO : Could not find ucf fragment for 'sip_data_processing' ID=0 (C:\Program Files(x86)\4dsp\Common\Firmware\Extracted\ml605_fmc126_modified_v1_0\star_lib\sip_data_processing\sip_files\sip_data_processing_ML605_0.ucf)[/i][/b]

About folder hierarchy, I kept the structure advised on stellar_ip.pdf and this one used by ml605_fmc126 firmware (cf.attachment).

I'll send you an email shortly with the archive of my project.

Best regards,
Alexandre
Dear Alexandre,


I checked your project, your ucf file in the sip_files is called sip_data_processing_ml605_0.ucf.ucf


I removed the last .ucf and then your design generates fine!


I assume you have the "Hide extensions for known file types" enabled in your Windows Explorer settings.


Best Regards,
Arnaud



Dear Arnaud,

Thanks you very much, I never looked at windows explorer settings if you have never told me so.

I have another problem now. I implement Xilinx IPs in my star (Digital Direct Synthesizer and Complex Multiplier), but there are missing in the generated ISE project in the output file. However I mention the folder path to acces to their xco files in the lst file. Is there something else to do? or should I do differently?

Another thing, my star have four external inputs. These inputs should be connected on some external pins of fmc126 star (adr_p_0, bdr_p_0, cdr_p_0 and dbr_p_0). If I call my nets with the same name as the fmc126's nets and I declare their localisation in one of both ucf file, they will be connected ?

best regards,
Alexandre
Dear Arnaud,

I fixed probelms mentionned on my previous post by myself . About Xilinx IP, I manually imported the ipcores and regenerated it. Otherwise, about external signals, I make some changes directly in the ISE project. But if you have something to generated automaticaly  the correct constellation design  by 4DSP GUI, I'm interested.

best regards,
Alexandre


Alexandre,


If *.xco file is in the lst file, it should be copied to the Src folder in the generated ISE project. Our 4FM Gui does not add *.xco files when it generates the ISE project. You need to manually add them. What we usually do is that we generates the all IPcores in the source folder and add the generated *.vhd or *.v files in the lst file. But we also include the *.xco and *.ngc files in the list file because when the user wants to change the IPcore, it can be easily updated in the generated star folder.


It may not be a good idea to use the same clock input connected to multiple stars. It will be better to modify the fmc126 star to have external outputs for your star.


Thanks,
Kyu
[font=arial][size=2]Hello,[/size][/font]

[font=arial][size=2]I am come back to you because I went further in my understanding of the fmc126 firmeware. I succeeded to implement my own star, and made almost what I wanted for data-processing.[/size][/font]

[font=arial][size=2]The fmc126 star use burst mode and this mode is blocking for the application I want to achieve (cf. attachment). Indeed I need to digitalize high frequency signals on a long period, in this way the burst blocking me.  The data-processing itself no need a long time lapse, but the fact that waiting for full fifos and send an arm command induce the lose of data from ADC. A data conversion on the fly should be better for my application and buffer data later to transmit by ethernet. Is there a way to switch the burst mode for a "continuous mode" ? Is there a fmc126 star without fifos or should I make one by myself ?[/size][/font]

[font=arial][size=2]Another thing, I remark that clocks signals from each channel are divided by 4 at the FPGA inputs. I use the sample frequency of 625 MHz and the ADC on two-channel mode, it seems to me that clocks without divider could be supported by Virtex 6. So in case I use two-channel mode and a sample frequency of 625MHz is it possible to keep exactly the clocks of each channel ? (I attached the clock tree dividers values that I implemented on software).[/size][/font]

[font=arial][size=2]Best regards,[/size][/font]
[font=arial][size=2]Alexandre[/size][/font]
Dear Alexandre,


We do not have streaming star readily available. We have implemented that for another project, some data recorder where we could stream data at 5Gsps on hardware memory we might have all the element you need but not available free of charge. Maybe it would make sense to ask sales about pricing/availability. Otherwise you will also need to slightly change the FMC126 star:


- Enable continuous mode, I believe a burst counter is implemented in the star. The idea would be to bypass this mechanism so it will do unlimited bursts.
- Indeed the internal FIFOs should be bypassed.
- It might be required to add extra data wormholes, the theoretical bandwidth of the data bus is 125MHz * 8 bytes ( 64 bit ). One sample is transferred as 2 bytes so as you can see, the bandwidth is not sufficient.


On the data routing side, the data routers are eating input data not connected to an output. You will also need to look at changing the buffering so the data of unconnected.


In a general point of view, you want to interleave channels into one stream and send that to the ML605 hardware DDR3. Then you would offload data from the DDR3 memory towards the host.


Obviously you have quite a few things to change or look into but this is normal. You can also ask 4DSP sales about a "reference design" closer to what you are trying to achieve.


I hope that helps,
Arnaud
About the clocking,


A clock of 2.5GHz is fed to the ADC chip. The ADC chip outputs a clock per channel along with the data. For 1, 2 and 4 channel mode the ADC chip receives 2.5GHz clock and outputs 1.25GHz clock with all the channels. In the firmware is a serdes 1/8 (to be confirmed in the source code).


About maximum speed of ioelement in V6, check Xilinx litterature it has this info. Typically you need a high speed grade device and such devices are not the one populated on the ML605.


Best Regards,
Arnaud
Arnaud,

Thank you very much for quick reply.
I contact the 4DSP sales.

Best regards,

Alexandre
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