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FMC151 ref. design in Vivado

Hello,


I would like to get  4DSP StellarIP reference design  kc705_fmc151 to work in Vivado 2014.3 and I wonder if I could get some advice in this forum.


So far I've imported the VHDL source, except for Xilinx IP modules, which I added in Vivado by hand, using original settings from reference design . The reasoning was that new IP comes with proper internal constraints for Vivado. I've imported pin-out constraints.  Clocking constraints were created from scratch, including creating several asynchronous derived clock groups.


I was able to generate a bit file and run it through tests with FMC15xAPP. Vivado still complains that there isn't a dedicated clocking  route from IDELAY2 to BUFG as I have mentioned previously here  - http://www.4dsp.com/forum/index.php/topic,2862.0.html. That was confirmed by Xilinx for me.


The design mostly works, bug the ADC ramp pattern test in FMC15xAPP reports 0.25 to 0.5 % error rate. I saved recorded ramp pattern and  there is an  occasional single bit error, typically in the same bit rank. Is it possible that align_machine does not produce optimum results in Vivado? Or could this error come from clock domain crossing?


I wonder if Vivado timing implementation is too optimistic and one needs to specify setup and hold constraints for  the I/O. Is there any documentation on FMC150/151 I/O timing parameters?


Thanks in advance for any advice ion this matter.




Luis,


Thanks for clarification.


I have few more questions related to reference design:


- Are dac_clock and dac_data outputs programmed to change simultaneously, i.e. with zero setup time? That's how code looks to me.
- looking at dac3283 datasheet, the minimal setup time is NEGATIVE 25 ps. Do I understand it correct that dac_data can be settling for up to 25 AFTER dac_clock transition, which would clarify the above question I have as well?
- Ref. design is set to output dac_data at 122.88 MSPS, while reading ADC data at twice that rate. Are there any particular technical limitations in the hardware or reference firmware I should be aware of if I am to double the dac_data sample rate to match ADC rate?





- Are dac_clock and dac_data outputs programmed to change simultaneously, i.e. with zero setup time? That's how code looks to me.

Yes that is what it looks like to me as well. This is just a reference design so if it works then it is considered good.

- looking at dac3283 datasheet, the minimal setup time is NEGATIVE 25 ps. Do I understand it correct that dac_data can be settling for up to 25 AFTER dac_clock transition, which would clarify the above question I have as well?

You have these two times :

START_TIME = CLOCK_EDGE_TIME - SETUP_TIME = 0 - (-25) = 25 ps
END_TIME    = CLOCK_EDGE_TIME + HOLD_TIME =  0 + (375) = 375 ps

Since the data is not changing within that window it works. The negative is good it means that the window starts after the clock edge.


- Ref. design is set to output dac_data at 122.88 MSPS, while reading ADC data at twice that rate. Are there any particular technical limitations in the hardware or reference firmware I should be aware of if I am to double the dac_data sample rate to match ADC rate?

Not that I am aware of.
Dear Sir,


I see that Luis took the extra miles to help you out, thanks for that Luis!


I assume we are good to close this topic for now?


Thanks,
Arnaud
Yes, you can close the topic. Thanks for all the info on reference design.
Just to update - the ref design seems to work fine in Vivado 2014.3 after doubling txclck* rates in dac3283phy.


I also assigned ASYNC_REG attributes to some signals in pulse2pulse module, that seems to help with closing SPI-related timing.  Is that correct approach?

Yeah. For clock domain crossing generally use set_false_path so the tools don't waste time trying to meeting timing on something that it shouldn't worry about. That would look like this:

# Generated clock used for SPI interface (system clock divided by 16)
create_generated_clock -name spi_clk -source [get_pins sip_fmc144_0/spi_wrapper_inst0/sclk_prebuf_reg/C] \
                                        -divide_by 16 [get_pins sip_fmc144_0/spi_wrapper_inst0/sclk_prebuf_reg/Q]

set_false_path -from [get_clocks spi_clk] -to [get_clocks clk_out2_ethernet_clock]
set_false_path -from [get_clocks clk_out2_ethernet_clock] -to [get_clocks spi_clk]

Thanks Luis. I basically did the same with the timing constraints that I posted above. I just used set_clock_groups -asynchronous in place of set_false_path, perhaps not separating every SPI clock domain into its own group, but async_reg seems to take care of other CDCs.


In any case, I got the ref design to work in Vivado with your help and the subject can be closed. 




This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.