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FMC176 without any reference design?

Dear all,

My name is Luciano. I have an FMC176 board and I have to connect it to a VC707 board. The VC707 Ethernet reference design works fine when it is alone. My problem is that inside the Virtex 7 I have to implement a big project and Xilinx ISE fails during the implementation, if I try merging the reference design with my custom project.
Can I use the board without using the reference designs? If yes, how can I do? I read the manual 4FM_Get_Started_Guide.pdf and the FMC176_user_manual.pdf but I couldn't understand how to make it work without the reference designs.

For example, in the Ethernet reference design I saw that for the DAC0 channel 0 there are the following signals: dac0_dci (differential clock lines from FPGA to FMC176), dac0_dco (differential clock lines from FMC176 to FPGA), dac0_p0 (14 differential lines for the data to be converted) and dac0_frm_p. On the FMC176_user_manual.pdf page 21, this last differential signal is described simply as "Frame going the 1st D/A converter". I really don't know what does it mean... How am I supposed to use such signal?

In general, I need to convert both a digital signal into an analog one and vice-versa. So I would like to connect to the DAC0 my digital signal and to take the digitalized signal from the ADC0

Thank for any help.

Regards,

Luciano

This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.
Dear Luciano,


We don't have such table no. But we have a open source reference design you could modify to create such a table as csv format. Last time I had to do that I have implemented a CSV file creation in SIPIF.cpp.


After running the reference design you would obtain a csv file will address/value for both writes and reads. This will provide you with a list of read/write required in order to bring the chipset up and running.


Best Regards,
Arnaud







Dear Arnaud,

my design is very big and I cannot match my design with the example design. I've implemented a uBlaze system with an SPI interface in order to drive the FM176 board.

We need only to configure the both the DAC 0 and 1 with the internal clock set to 2.4 GHz and the ADCs set with a 500 MHz clock.

Could you please tell me which SPI commands to deliver to the FMC176 in order to drive it in the configuration stated above?

Thank you.

Best regards,

Luciano
Dear Luciano,


http://www.analog.com/static/imported-files/data_sheets/AD9119_9129.pdf? There is a notion of frame in there. But yeah we tend to not document everything as there is a reference design someone can run in real world, adding chipscope if required or simulate. These are really usual firmware development cycles working from a reference design.


As far as the implementation error, you might need to constraint the design better or change the clocking scheme.


I hope that helps,
Arnaud