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FMC 104 - Zedboard ADC channel interface

[font=calibri]Dear 4DSP Support:[/font]
[font=calibri]I have a system that consists of a FMC104 connected to the FMC-LPC interface of a ZedBoard.  I have configured that AD9510 to provide a sampling rate of 100MHz to all four ADC channels with identical frequency and phase.  The intent is to sample faster but I started with a 100MHz rate.[/font]
[font=calibri]My initial FPGA design used a dedicated MMCM for each ADC channel to regenerate a 100MHZ clock and provide proper source synchronous timing at the IDDR elements use to convert the 7-bit DDR bus into a 14-bit SDR bus.  I received each ADC channel clock with an IBUFGDS and each DDR data bit with a IBUFDS.  A portion of signal processing fr each channel is done in the local channel clock domain and after integration/decimation (factor of 64), FIFOs are used to cross from the local ADC channel clock domain into a common PL fabric clock domain for further signal processing.[/font]
[font=calibri]The problem with this approach is that MAP complained about the sub-optimal location of the clock I/O pads and the associated MMCM tiles located around the corners of the chip.  Since the physical location of the clock inputs is dedicated by the FMC104 design and the implementation of the FMC-LPC on the ZedBoard, I have no control over this.  I was able to get around the MAP errors and demote them to warnings by using a "dedicated_route" constraint for each of the four MMMCM clock inputs.  However, although I do seem to be getting valid ADC data in SDR format, I am not confident that timing will be robust with further implementations.[/font]
[font=calibri]I have noticed that the four ADC channel clocks appear to be reasonably well time-aligned and it makes sense to me since the ADS62P49 input clocks are driven by the AD9510 that is configured for identical frequency and phase.  Can the clock form one ADC channel be used to supply a single MMCM that could serve for all four ADC channels?  This would allow a better placement of the clock pad and MMCM.[/font]
[font=calibri]If not, are there any other strategies that improve routing if all four MMCMs are used or with fewer MMCMs?[/font]
[font=calibri]Thank you for your support in advance,[/font]
[font=calibri]Craig[/font]


Craig,


What I meant was the VHDL sources extracted from the 4DSP BSP. I believe you have all source codes.


Thanks,
Kyu
Hi Kyu:

Can you please email me the source to which you refer or give me a link.

Thanks,

Craig

Craig,


The provided VHDL sources are all we have. I think you should open the webcase from the Xilinx. They will help you out better on your current issue.


Thanks,
Kyu
Hi Kyu:
I am using only the CLK_AB pair drive a single MMCM and its CLK0 output is set to regenerate the 100MHz input clock is then used by all four groups of IDDR to latch the DDR data and convert to SDR.  I am assuming that the data to clock skews across the PCB are very close to the same so that the deskewed clock that is present at the IDDR flops is placed in the center of each odd and even data window.  I am not using any IDELAY elements because I though the assumptions I made above are valid.
I see what maybe valid data on one of two channels that I feed through a matched splitter but the other channel is bad data.  I am guessing that I am not constraining the design properly so that the IDDRs can properly clock data on both edges. 

What am I missing here?  Do you have any sample VHDL and constraints for interface with a Zynq or other Artix fabric from Xilinx?

Craig,


ADC clocks in zc702 are CC pins. They are the optimum clock pins. If you are tyring to use one clock source to feed inputs of 4 MMCMs, I don't think it's a good approach. When you use the single clock source, I think you need to use one MMCM and then output of MMCM can be used to feed all other ADC channels. Please refer the Xilinx user manuals for more detail.


Thanks,
Kyu
Hi Kyu:

I still do not believe that I am getting correct ADC data from all the channels in my latest FPGA builds.  Most likely, I am not properly constraining the paths adding in data delay.
For example, if I feed in a 20MHz sine-wave at -15dBm into channels A and C of the FMC104 and look at the raw ADC samples after conversion to single data rate and sign extended to 16 bits, I see that the channel A and channel C data looks sinusoidal but the amplitude of channel A  is about 1/20 of expected??"?  It is even more perplexing because I have used the CLK_AB signal to provide the common clock and I would have thought that the channel A data would be reliable. In my most recent design I feed the 100MHz CLK_AB signal into one of the the Zynq7020's MMCMs and generate what I believe is a source de-skewed 100MHz clock that I use for all four channels.
I have tried other clocking approaches with four MMCM where I used all four ADC channel clocks but I had to use "dedicated_route" constraints because the path form the clock pads to the MMCM around the chip were not optimum.  This caused be concern that timing would not be consistent over routing and led me to want to use only one ADC channel clock for all four channels.
Am I making a fundamental error in the way I am trying convert the DDR data to SDR because I think you agreed in your last post that only a single ADC channel clock is required.  I have not done much work with DDR-to-SDR conversion and I wonder if my simple PERIOD constraint is not adequate for ensuring that the IDDR blocks in the FPGA can properly clock data in on both edges. 
I would be happy to send you a portion of my VHDL or receive any guidance on properly constraining my design.

Thanks,

Craig

Hello Craig,


Yes, you can use the one ADC clock to supply all four channels.


Thanks,
Kyu
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