Start a new topic

FMC151 ref. design in Vivado


I would like to get  4DSP StellarIP reference design  kc705_fmc151 to work in Vivado 2014.3 and I wonder if I could get some advice in this forum.

So far I've imported the VHDL source, except for Xilinx IP modules, which I added in Vivado by hand, using original settings from reference design . The reasoning was that new IP comes with proper internal constraints for Vivado. I've imported pin-out constraints.  Clocking constraints were created from scratch, including creating several asynchronous derived clock groups.

I was able to generate a bit file and run it through tests with FMC15xAPP. Vivado still complains that there isn't a dedicated clocking  route from IDELAY2 to BUFG as I have mentioned previously here  -,2862.0.html. That was confirmed by Xilinx for me.

The design mostly works, bug the ADC ramp pattern test in FMC15xAPP reports 0.25 to 0.5 % error rate. I saved recorded ramp pattern and  there is an  occasional single bit error, typically in the same bit rank. Is it possible that align_machine does not produce optimum results in Vivado? Or could this error come from clock domain crossing?

I wonder if Vivado timing implementation is too optimistic and one needs to specify setup and hold constraints for  the I/O. Is there any documentation on FMC150/151 I/O timing parameters?

Thanks in advance for any advice ion this matter.

I am not sure I understand what is going in the screen capture, but if I understand correctly the overall issue is that you are trying to port the KC705_FMC151 design into Vivado. We currently don't support that and I can only offer basic advice.

It sounds like you almost have it working expect you get occasional bit flips on the data you are receiving. Usually that happens when the IDELAY tap values aren't set correctly so my advice is first confirm that the alignment machine is working.

So look in ads62p49_phy.vhd, there are these delay values (signal delay_value_a, delay_value_b, delay_value_c). Try reading those out in the software that happens in the function fmc15x_adc_init(). The tap delay can be from 0 to 31. What values are your tap delays set to when you capture data? Are you doing manual or auto training try both and see if you get better results with one or the other.

Try adjusting the following values when doing auto trainning (in fmc15x_adc_init)

            AdcPreTrainingCount = 0;
            clk_delay_training = 2;

Those determine where it will start looking for a valid window. Make the 2 a 0 or a 10. See if that makes a difference.

Try adjusting the following when doing manual training (in main)

        printf("Found KC705 hardware\n\n");
        tapiod_clk = 0x00; tapiod_data = 0x00;

Try just incrementing the clock IDELAY value by increments of 5 and see if the data you get starts getting better or worse. That finds the window where the data is good manually. 

Here's another snapshot with a train of spikes in the same linear sweep capture
I'm attaching an ILA snap shot of a particular spike during linear pattern generation. It look to me that  iodelay outputs there transition at the same time while there's jitter down stream, in cha_sdr_se bus. I wonder though if the probe can capture idelay jitter, since the data is coming at double the clock rate there?
I put some debugging probes and I can see the glitches appearing as early as in ads62p49_phy. I was not able to probe IDELAY ins and outs due to "routing congestion". It seems to be  more glitchy with debug probes attached.
Perhaps you can look at the data sheet of the ADC and instead of doing the ramp pattern you can do all 1's or all 0's or constant pattern and see if you get a bit flip. With a constant pattern you can trigger on the bit flip. Also try to monitor what is going on with the IDELAY which values is it picking is it consistent? If you are getting random errors once in a while the most likely cause is the IDELAY isn't getting set correctly.

Thanks for looking into this issue.  Is there an easy method to track a bit error that only occurs one out of 500 or so times, at random?

Vivado does not report timing violations except for couple  sub-ns hold violations in amc7823_ctrl on clock domain crossing to SPI clock, but the board seems to report correct voltages and temperature in the app nervelessness.

Here's the timing constraints that I used with reference design in Vivado:

[code]create_clock -period 4.069 -name clk_ab_p_0 -waveform {0.000 2.035} [get_ports clk_ab_p_0]
create_clock -period 4.069 -name clk_to_fpga_p_0 -waveform {0.000 2.035} [get_ports clk_to_fpga_p_0]
create_clock -period 8.000 -name phy_rxclk_0 -waveform {0.000 4.000} [get_ports phy_rxclk_0]
create_clock -period 5.000 -name sysclk_p_0 -waveform {0.000 2.500} [get_ports sysclk_p_0]

create_generated_clock -name sip_fmc151_0/fmc151_if_inst/ads62p49_ctrl_inst/sclk_prebuf -source [get_pins sip_mac_engine_0/mac_engine_inst/brd_clocks_inst/pll0_inst/U0/mmcm_adv_inst/CLKOUT1] -divide_by 16 [get_pins sip_fmc151_0/fmc151_if_inst/ads62p49_ctrl_inst/sclk_prebuf_reg/Q]
create_generated_clock -name sip_fmc151_0/fmc151_if_inst/amc7823_ctrl_inst/sclk_prebuf -source [get_pins sip_mac_engine_0/mac_engine_inst/brd_clocks_inst/pll0_inst/U0/mmcm_adv_inst/CLKOUT1] -divide_by 16 [get_pins sip_fmc151_0/fmc151_if_inst/amc7823_ctrl_inst/sclk_prebuf_reg/Q]
create_generated_clock -name sip_fmc151_0/fmc151_if_inst/cdce72010_ctrl_inst/sclk_prebuf -source [get_pins sip_mac_engine_0/mac_engine_inst/brd_clocks_inst/pll0_inst/U0/mmcm_adv_inst/CLKOUT1] -divide_by 16 [get_pins sip_fmc151_0/fmc151_if_inst/cdce72010_ctrl_inst/sclk_prebuf_reg/Q]
create_generated_clock -name sip_fmc151_0/fmc151_if_inst/dac3283_ctrl_inst/sclk_prebuf -source [get_pins sip_mac_engine_0/mac_engine_inst/brd_clocks_inst/pll0_inst/U0/mmcm_adv_inst/CLKOUT1] -divide_by 16 [get_pins sip_fmc151_0/fmc151_if_inst/dac3283_ctrl_inst/sclk_prebuf_reg/Q]
create_generated_clock -name sip_fmc151_0/fmc151_if_inst/fmc151_ctrl_inst/O1 -source [get_pins sip_fmc151_0/fmc151_if_inst/fmc151_ctrl_inst/ext_trigger_prev1_reg/C] -divide_by 1 [get_pins sip_fmc151_0/fmc151_if_inst/fmc151_ctrl_inst/ext_trigger_prev1_reg/Q]
create_generated_clock -name sip_mac_engine_0/mac_engine_inst/ge_mac_stream_inst/eth_mdio_inst/sclk_prebuf -source [get_pins sip_mac_engine_0/mac_engine_inst/brd_clocks_inst/pll0_inst/U0/mmcm_adv_inst/CLKOUT0] -divide_by 16 [get_pins sip_mac_engine_0/mac_engine_inst/ge_mac_stream_inst/eth_mdio_inst/sclk_prebuf_reg/Q]
create_generated_clock -name phy_txc_gtxclk_0 -source [get_pins sip_mac_engine_0/mac_engine_inst/ge_mac_stream_inst/gmii_eth_tx_stream_inst/oddr_tx/C] -divide_by 1 [get_ports phy_txc_gtxclk_0]

set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks clk_ab_p_0] -group [get_clocks -include_generated_clocks clk_to_fpga_p_0] -group [get_clocks -include_generated_clocks sysclk_p_0] -group [get_clocks -include_generated_clocks phy_rxclk_0]

The I/O timing would be in the ADC documentation. If you are getting a single bit error I would track down where the error is happening with chipscope (or the Vivado equivalent, hardware manager).  Look at what comes out of the SERDES. Are you meeting timing?  The conversion between ucf and xdc is not always correct and you should manually check that they are correct.