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kc705_fmc150.dsn - no wormhole connections?

When I open kc705_fmc150 reference design from FMC150 BSP in Stellar IP, the stars do not seems to be connected with wormhole connections? There are stars with labeled input/output pins, but that's it. Am I misunderstanding something or am I supposed to connect them myself as an exercise?  Similarly, only few of the needed wormhole connections appear on kc705_trainmat design.

Please advise. 

I figure the labels are WH connections. My bad.

A follow-up question - Stellar IP does support Vivado, but most of the TRD sips, including sip_fmc150, are not compatible with Vivado and will not work for Vivado generation, isn't it?
Dear Sir,

Yeah, these designs with labels where imported and the tool automatically place labels. Design directly created in the new tools have the connections as wires.

StellarIP does support Vivado indeed but we are not going to bring Vivado support for target still supporting ISE. In other word, we are already supporting Vivado for very large Virtex 7 devices not supported by ISE. Same goes with Ultrascale, they will only be supported by Vivado.

Support for Vivado is likely about to ad XDCs but the StellarIP supports Vivado already!

Best Regards,
Dear Arnaud,

Could you clarify if sip_fmc150 that comes with FMC150 BSP supported in Vivado? Same question for 400_kc705_trainmat TRD.

Where can I find comprehensive Stellar IP info in general? I went through documentation that came with BSP, i.e. 2011 SIP user guide, 2010 SIP quick start, more recent 4FM starter, various TRDs, but still have many questions. There's a mention of online training, what does that involve?

Dear Ted,

The FMC150 and TRD come without Vivado support; we have started supporting Vivado very recently on projects involving large V7 FPGAs. The support of older firmware for Vivado is not yet planned. There is a Xilinx document covering migrating ISE projects to Vivado., chapter 3 is the chapter to focus on.

The online training is something to be discussed with our sales department where a specific training is prepared, the user connects to one of our machine and one of our employees is demonstrating the tool and answering question, etc..

Feel free to your questions in separate topics and we will try to answer these questions as good as we can!

Best Regards,

I'll get in touch with our sales contact at 4dsp about training than, see if he replies.
Dear Arnaud,

Would you let us know when .xdc files will be added to kc705-FMC150 reference design (if I understand you remark that you're about to add them correctly)?
Dear ted

we have no plans to update our reference designs to support Vivado on the short term. You can generate the ISE design and import this to VIVADO and you should create your own XDC file based on the UCF file that was generated. Xilinx offers a tool in "plan ahead" to write an XDC from UCF file. This is the "write_xdc" command to be used from the tcl commandline. This process is described in the ug911-vivado-migration.pdf from Xilinx

best regards,
This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.