PLL is not locked on my FMC150 board, neither the PLL status bit in the register nor the pin.
I am using the firmware extracted from the BSP package. The PLL is not locked. But the CLK-to-FPGA clock is measuring 245MHz. It looks like the DAC clock is around 491MHz by scoping on R70/R71 resistor’s pad. And ADC clock is around 166MHz by checking CLK_AB on FPGA. I think they are the expected numbers.
I have got the following readings from internal registers of CDCE device:  0x683C025 0 (Hex)  0x6800027 1 (Hex)  0x8382000 2 (Hex)  0x6800000 3 (Hex)  0xE980000 4 (Hex)  0x6800000 5 (Hex)  0x6800000 6 (Hex)  0x8340000 7 (Hex)  0x6800009 8 (Hex)  0x680500C 9 (Hex)  0x08FC270 A (Hex)  0x8000040 B (Hex)  0x60009B0 C (Hex) Status4 INDET_AUX It indicates that a clock is present at AUX-input (Y9) , when set to 1 RAM(Read Only) Status5 INDET_VCXO It indicates that a clock is present at VCXO-input , when set to 1 RAM(Read Only) Status6 PLL_LOCK It indicates that the PLL is locked when set to 1 RAM(Read Only)
Then I calculated the dividers using the equation…
Fvcxo/Fref = P*N/(R*M)
Here with Fvcxo = 491.52MHz, Fref = 100MHz, P = 8, N = (575+1), R = 1, M = (624 + 1), both sides are not equal. N should be (3839+1) to make them equal. So I changed the initial coefficients for the firmware to configure the FMC150 board on reset. And then the register value at 0xA is 0x3BFC270A. But the PLL is still not locked.