Hi, I'm a bit confused about the current divider settings according to the user guide: For a reference of 100MHz, the divider of 625 gives 160kHz. This matches with the recommended phase detector frequency. But for the standard 491.52MHz VCXO the divider is set to 8x576=4608, which gives approx. 106.6667 kHz. This is wrong in my opinion, since both frequencies at the phase detector should match, shouldn't they? In my VHDL reference design, the divider is set to 8x384=3072, which is correct. So, did I miss some errata for the user guide?!
over 8 years ago
Our reference application is overwriting all settings and is programming 384 for the standard 491.52MHz VCXO. This is indeed the correct value.