I have similar problem as you. We have FMC230 and FMC126, which is DAC and ADC respectively.
I think it is difficult to directly bring up DAC and ADC boards without the reference designs of 4DSP. So I reuse and modify some code, and use ROM to collect the initial command form the Ethernet. It finally works.
If you want to know more, e-mail me (firstname.lastname@example.org), and we can have more discussions.
I am Jerry Huang, an engineer in Siliconimage, San Jose. We bought DAC board (FMC 230)and ADC board(FMC12x) from your company .
We tried to use the two boards on our own FPGA emulation system, which is based on two Virtex-7 cores. Since it being a new system, I plan to directly implement control logics using Verilog on one of Virtex-7s to bring up DAC and ADC boards, instead of being on the environment your company’s provided. But we are stuck in an issue regarding the bring-up of FMC230. The details are shown as follows.
(1)In order to configure the DAC board(FMC230), we’ve implemented a SPI master in FPGA with your company’s spec shown in FMC 230 User Manual, including three wires for SPI.
(2)With probing the output signals from FPGA on our emulation system, the behavior of SPI output from FPGA has been proved to be correct.
(3) In order to check if the SPI output has been sent into the DAC board successfully, I conduct an experiment for verifying the communication between DAC board and our FPGA. I sent two commands from our FPGA to DAC board for writing and reading back CPLD register value. The first command is served to write certain value (0x08) into register00 of CPLD for resetting clock tree. Then, the second command is served to read back the value written with the first command, which is supposed to be 0x08, but actually 0x00. I checked every potential issue, but found no answer on that. Based on the observation, I guess, there is no talk happen between the two devices.
So I have a couple of questions below.
(1) Is it reasonable to guess that there is no talk between the on-board CPLD and our FPGA based on what I mentioned before? If so, what is the reason?
(2) Is there any pre-work for FMC board (such as the reset action for dac board or cpld) before reseting on-board clocktree and dac chips? Because I knew there were some reset action for clock tree and DAC chips in CPLD_INIT part in the C code.
(3)The C code in the relevant package does provide some information on how to start up FMC board. However, since we plan to write Verilog code to control the FMC230 and FMC12x on the FPGA, we need more details regarding how the DAC board and ADC board work, including the entire start-up sequence and other operations. Could you give us any support for this case?
Please let me know if more information is needed. BTW, since our project deadline is coming, I really hope your immediate response.