Has this been resolved and if so how? Is it pertinent to my problem getting an ADC clock from the FMC161?
I reviewed figure 8 and table 14 multiple times. I'm setting the bit 2 in reg 0x01 to '1' correctly. It would be nice to be able to read back the contents of the reg 0x01, but it's not supported.
Is it possible for 4DSP to test this option on the FMC160?
If you look at figure 8 in the UM you'll see that the ADCLK948 of the ADC clk has two inputs. Did you configure the ADCLK948 to use the correct input( CLK1)? This is a register setting of the CPLD (reg 0x01, bit 2), refer to table 14 in the UM.
Ingmar van Klink
I configured the FMC160 to run the ADC at 700 - 1100 MHz and DAC at 1400 - 2200 MHz, which is referred to as the "low range" in the User's Manual. I've set up the clocks as follows:
reference source = internal
D/A clock source = internal
A/D clock source = DAC clock divided by 2
As I understand it, both ADC and DAC are using the auxiliary output of the ADF4351. I'm able to see the correct clock frequency from the DAC, but there's no clock coming from the ADC.
I've tried two different FMC160 boards and got the same results of no ADC clock in "low range" mode.
Am I not configuring the clocks correctly? Is the clock divider chip not working? Please advise.