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## FMC150 clock frequencies

Hi,

I am very confused on how to confige the CDCE on my FMC150 board. the VCXO max frequency is 491.52MHz , I want to know  weather i can change the VCXO frequency by change the M or N or  not .  The VCXO is fixed?
I calculated the dividers using the equation…

Fvcxo/Fref = P*N/(R*M)

a.Here with Fref = 100MHz, P = 8, N = (383+1), R = 1, M = (624 + 1), the output divider 4 is 1, then  the CLK-to-FPGA clock is measuring 491.52MHz.I think the configuration is correct and the PLL is locked. it means that the  Fvcxo =  491.52MHz  .

b. If i change the configuration .  with Fref = 100MHz, P = 4, N = (767+1), R = 1, M = (624 + 1), the output divider 4 is 1, then  the CLK-to-FPGA clock  also is  measuring 491.52MHz.

c.If i change the configuration . with Fref = 100MHz, P = 4, N = (383+1), R = 1, M = (624 + 1), the output divider 4 is 1, then  the CLK-to-FPGA clock   is  measuring 491.52MHz. but it should be  491.52/2 = 245.62 ? . why it still 491.52Mhz, I have read the registers, the configuration is changed just like what i want it . but i got a Unreasonable frequency .

Can anyone explain this? and tell me  how to configure the registers .

Thanks

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