FMC 168 - CPLD registers are not clear (0x04- 0x07 --- Appendix C - CPLD Register map from manual)
started a topic
almost 6 years ago
created microblaze system with I2C ip core and sending the data through
I2c protocol(SDK) to CPLD register (command, control) and are using FMC168 steller IP generated VHDL project to
monitor ADC 16bit data at the SERDES output.
Can we get to know ethernet protocol which is used between 4FM GUI & Steller IP VHDL project, so that we can develop our own to configure CPLD, ADC chip & clock tree.
Need sequence of register setting for CPLD, ADC, Clock tree (.cpp) for internal clock 250Mhz .